Start date: 20 January 2026
Duration: 4 Days, 9:15 am to approx. 4:00 pm each day
Location: Online course
Certificate: N/A
Cost: Members € 550; Non-members € 825
Course code: N/A
Programme overview
This 4-day course is an introduction to the SystemVerilog language, focusing on verification of digital RTL designs. The course material has been completely revised for the 2026 edition incorporating feedback received from prior editions. The ideal attendee is a verification engineer who has experience with the Verilog language and wants to deploy a modern object oriented approach to testbench development. It is delivered as an interactive remote learning course with a maximum of 12 participants to maintain high quality training.
Learning outcomes
Participants will be able to develop object oriented SystemVerilog test benches to verify digital RTL designs. This course is also an ideal precursor to studying the Universal Verification Methodology (UVM).
Who is the course for?
Digital RTL verification engineers. A knowledge of the Verilog language is a prerequisite.
Schedule
Day 1
Modern Testbench Architecture
Transaction Level Modeling
User Defined Types
Static and Dynamic Casting
Resolution Functions
Time Resolution
Packages
BFM Style Interfaces
Dynamic Threads
Thread Synchronisation
Inter-process Comunication
Day 2
UML Diagrams
Class Constructors
Deep and Shallow Copying
Transaction Objects
Sharing Property Values
Virtual Interfaces
Class Inheritance
The Composition Pattern
Data Hiding
Class Parametrisation
Day 3
Constrained Randomisation
Constraint Blocks
Implication and Weighting
Hard and Soft Constraints
Randomising Program Flow
Purpose of Functional Coverage
Elements of Functional Coverage in SystemVerilog
Coverage Methods
Day 4
Immediate and Concurrent Assertions
The SystemVerilog Timeslot
The Elements of an Assertion
Implication
Repetition Operators
System Functions
Relating Sequences
Property Blocks
Local variables
Reusing Properties and Sequences
Assertion Directives
The bind Construct
Trainer Profile
Nigel Woolaway is President and co-founder of Leading Edge based in Milan. Nigel initially worked as a designer on military and commercial communication systems and started developing verification methodologies for digital ASIC and full custom designs in 1983. He has since held various engineering and management roles in the field of design and verification at OEMs and EDA providers. Nigel has trained over a thousand engineers on three continents in the usage of VHDL, Verilog, SystemVerilog and UVM and consistently receives very positive feedback on his course delivery. In addition to training Nigel provides consulting services on UVM testbench development to companies in Europe and the Middle East.
This course was previously held in 2023 on: 23 – 26 Oct and 21 – 24 Feb 2023 and 4 successful reruns in 2022: 7 – 10 Feb, 7 – 10 Mar, 28 – 31 Mar and 30 Aug – 2 Sept. 2022 and 3 reruns in 2021: 8th – 11th Mar, 10th – 13th May and 18 – 21 Oct.
Please email training@midasireland.ie for further queries or to book places
