SAR ADC Design Workshop

Start date: 15 May 2023

Duration: 5 Half Days, 15, 17, 19, 22 & 24 May 2023, 9am - 1pm each day

Location: Online course

Certificate: N/A

Cost: Members € 500; Non-members € 750

Course code: N/A

Programme overview

This workshop is a highly interactive training course in the art and craft of switched capacitor SAR ADC design. The workshop will take participants through the design of a 10-bit Successive Approximation (SAR) ADC on a low cost 180 nm 1.8 V CMOS process using switched capacitor techniques. It will consist of a blend of learning approaches including concept and theory lectures, hands-on design and lab simulation exercises, quizzes, Q&A, demonstrations. By the end of the workshop, each participant will have gone through the process of modelling, building, and simulating a fully functioning CMOS 10-bit successive approximation A/D converter. Online support will be provided to facilitate participants to complete any lab exercises during the workshop and for up to 4 weeks afterwards.
To meet demand a re-run is scheduled for 15, 17, 19, 22 & 24 May 2023 after previous rerun on 28, 30 Mar, 1, 4, 6 Apr 2022 and the pilot course on 8,10,12,15 and 17 Nov 2021

Learning outcomes

* Interpret and evaluate data converter performance specifications
* Simulate and evaluate behavioural models for mixed signal circuits
* Simulate and evaluate CMOS switched capacitor circuits
* Design and simulate a SAR ADC behavioural model
* Evaluate and simulate a CMOS SAR ADC using switched capacitor techniques

Who is the course for?

This workshop is ideal for junior analog/mixed-signal design engineers but will also meet the needs of more experienced engineers in other roles, for example digital system design engineers, verification engineers, physical design engineers, test engineers.


DAY 1: Data converter fundamentals, MOS switch characteristics, switch errors, D/A settling time, data converter performance specifications, SAR ADC algorithm.
Labs: Voltage mode DAC, D/A behavioural model, Comparator behavioural model.

DAY 2: SAR logic design, MOS capacitors and switches, charge injection and clock feedthrough, behavioural SAR ADC design & simulation.
Labs: Switch charge injection and clock feedthrough, behavioural SAR ADC.

DAY 3: Dynamic circuits, sampling circuits, reduction of charge-injection & clock feedthrough, switched capacitor (SC) DAC, settling time, split array technique, kT/C noise. Labs: Charge redistribution, SAR control logic. 10-bit split-array behavioural model.

DAY 4: SC SAR ADC signal sequence analysis, charge-injection & clock feedthrough considerations, differential topology, parasitic capacitance, bottom plate sampling.
Labs: 10-bit CMOS switched capacitor SAR ADC.

DAY 5: Introduction to sampled data comparators, offset cancellation, introduction to digital calibration, other design considerations (DFT, reference settling, 1 V design, error budget).
Labs: 10-bit SAR ADC Test Bench, sampled-data comparator.

Trainer Profile

Ken Deevy was a senior design engineer at Analog Devices and spent over 10 years involved in the design and development of a wide variety of analog mixed signal circuits, including high-resolution and high-speed data converters, precision comparators, analogue signal conditioning circuits, voltage references and oscillator circuits. Ken has over 25 years of experience as a senior lecturer, educator and researcher in higher education. He holds 4 patents and co-awards in the field of microelectronics. Ken holds a Bachelor degree in Electronic Engineering, a Master’s degree in Electronics and Computer Engineering and a Master of Higher Education degree from the University of Sheffield.

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