Advanced Digital Design

Start date: 24 October 2023

Duration: 3 Days

Location: Online course, 11am - 6pm each day

Certificate: N/A

Cost: Members € 600; Non-members € 900

Course code: N/A

Programme overview

This 3-day Advanced Digital Design training class is intended for experienced digital IC designers. It will teach & demonstrate Advanced Design techniques mostly using Verilog while adding some new SystemVerilog features. Techniques used will emphasize efficient, synthesizable, RTL coding techniques.
This course is being held on 24 - 26 Oct 2023 after reruns in 2022 held on 20 - 22 April and 9 - 11 Nov. It was previously held in 2021 on 30 Nov - 2 Dec and in 2020 on 18 - 20 May, 26 - 28 May and 29 Sep - 1 Oct. It will be delivered entirely online. The course tutor, Cliff Cummings, is based in Utah, 7 hours behind Irish time, so the course will be held each day from 11am to 6pm.

Learning outcomes

  • Advanced Digital Design techniques
  • Efficient, synthesizable, RTL coding techniques

Who is the course for?

Experienced digital IC designers.


3 days of advanced design theory and lab practicals, covering the following topics:

• SystemVerilog for Advanced Digital IC Design
– Review of Important Verilog Coding Guidelines
• Latches & Priority Encoders
• Combinational Logic I
• Implicit .* and .name Port Instantiation
• Combinational Logic II
• Sequential Logic Design Techniques
• Advanced Design Topics
• Synchronous & Asynchronous Reset Design
• Introduction to SystemVerilog Interfaces
• Finite State Machine (FSM) Design
• Design for Reuse / IP Design
• Multi-clock Clock Domain Crossing (CDC)
• Multi-clock FIFO Design
• Design For Test (DFT) Techniques

A detailed course syllabus in PDF format can download by clicking on the “Full Course Details” link in the image above.

Trainer Profile

Cliff Cummings has taught expert Verilog, SystemVerilog and OVM/UVM Verification to thousands of engineers world-wide since 1992 and has presented more than 50 papers on topics related to Verilog, SystemVerliog, synthesis and verification. More than 25 of Mr. Cummings’ works have been voted “Best Paper” at various conferences.

Mr. Cummings, was a member of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog Standards Groups from 1994 to 2012, and has received IEEE awards acknowledging his contributions towards developing these important IEEE and Accellera Verilog & SystemVerilog Standards.

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