Start date: 18 December 2025
Duration: 12 classes over Dec 25 to June 26
Location: Online course, Thursdays 4pm to 7pm for 12 sessions
Certificate: 10 ECTS
Cost: Members € 950; Non-members € 1,425
Course code: N/A
Programme overview
This 12 session CPD module will be held over 25 weeks, 18th Dec 2025 to 25th June 2026.
(This CPD module has been provided over an extended time to cater to practising Engineers that have a busy workload already and find the assessment workload very difficult over an intense 12 week programme).
It will allow graduate engineers and practising digital design engineers to upskill such that they can become more versatile contributing digital designers within a team environment from day 1.
The average participant workload on this CPD module will be 11 hours (for some it will be more and for some less) per session. The lectures and tutorials will be recorded and put online.
This is a follow on to the Digital IC Design CPD, which focused on core design and essential minimum Verilog skills. This CPD module extends that experience with exposure to more complex design examples, more extensive SystemVerilog syntax and including synthesis and reporting, examples and scripts.
It will involve more (for example) clock domain crossing assessments, Bus arbitration and bridging applied to APD, AHB and/or AXI interconnects
This MIDAS Skillnet programme is cofunded by the Government of Ireland and the European Union.
Visit www.eufunds.ie
Learning outcomes
On completion of the module, participants will be able to:
A) Design Clock Domain Crossing solutions to digital design problems.
B) Design solutions that adhere to Reset Domain Crossing protocols.
C) Use specify and assertions appropriately in their design RTL.
D) Implement Data protection on data transfer if required.
E) Set Constraints and Script a basic synthesis flow.
F) Understand the issues around and the basics of the design a basic APB/AHB/AXI crossconnect/bridge.
Who is the course for?
Working FPGA/ASIC design engineers who may not be familiar with all the aspects of the design flow or who want to deepen their knowledge. They will have used verilog and a simulator already but their experience might be limited.
Ideally the participant will have already successfully completed the Digital IC Design CPD or have equivalent prior project experience.
To apply for this level 9 module applicants will normally hold a 4-year degree in electronic engineering or cognate discipline. However, prior suitable industry experience may be taken into account.
Schedule
Context and Background Material: Overview of the extent of Digital Design space and Technology for implementation.
Verilog1 — Quick Review of Essentials: Review of logic elements. Basic Verilog Modeling of combinational logic, synchronous logic and FSMs.
SystemVerilog for Design: SystemVerilog Constructs for RTL Code with examples. Logic, Packed Structs, Enumerated types, Typedef, System verilog interfaces, Packages, Enhanced arrays(dynamic and associative) and queues.
Specify (timing)/ Assertions for functional Check: Specify and Assertions syntax and examples and related coverage points, groups.
Clock Domain Crossing: What it is, example Design and code and constraints.
Participant does worked assignment.
Reset Domain Crossing: What it is and example Design, code and example constraints.
Data Protection: In Memory – parity and ECC implementation, Buses — parity and ECC, Networks — CRC.
Design — Pipelining: Improving performance with pipelining. Example design using pipelinig.
Design — Bus Interconnect: Designing APB, AHB or AXI Bus Interconnect Solutions. Bus Arbitration, contention, FIFO queues, outstanding transactions.
Design — Real Time: Architectural Considerations, Bottlenecks. Dataflow. Queuing with FIFOs. Backpressure. Example using analysis of basic dataflow and congestion in Ethernet switch or similar.
Low power design Techniques: Clock gating, power gating. Logic Elements to support isolation, level shift etc.
Clock tree synthesis. Simulation for power analysis.
Logic Synthesis: Overview of Synthesis Logic — Minimization, Technology mapping, Timing Optimization.
Examples of mapping to specific technology library, constraints and scripting.
Timing Optimization: Reporting of timing analysis.
Trainer Profile
Richard Gahan is currently a Lecturer in Digital Design at TU Dublin, where he leads the MEng in Electronic Systems Design which has a major component in digital design and architecture. Previously Richard has held a number of positions in industry as Design Engineer, Project Leader, Design Architect, Design Centre Manager and Consultant Engineer.
Richard holds 12 patents is different areas of digital design, and has published research papers in areas of digital design and efficient video processing. Richard has taught courses in digital design to thousands of students and industry courses over several years.
Email training@midasireland.ie for bookings and queries
