SystemVerilog for Design

Start date: 07 October 2024

Duration: 3 Days, 9:15am to approx. 4:00pm each day

Location: Online course

Certificate: N/A

Cost: Members € 500; Non-members € 750

Course code: N/A

Programme overview

This 3-day course is an introduction to the SystemVerilog language for IC design engineers. It starts with a review of Verilog RTL design techniques, then introduces the many enhancements in SystemVerilog that make capturing RTL design intent easier. Finally the course introduces SystemVerilog Assertions, a powerful methodology to help validate design behavior. The course is intended for IC design engineers with some prior RTL experience who wish to learn SystemVerilog. It will be delivered as an interactive remote learning course with a maximum of 12 participants to maintain high quality training.
This course is rerun frequently to meet demand with the upcoming reruns on 12 - 14 Feb and 20 - 22 May and 7 - 9 Oct 2024 after a rerun on 9 - 11 Jan and 2023 reruns on 10 - 12 Jan, 24 - 26 April and 26 - 28 Sep 2023 and following 5 previous reruns in 2022 and 2021 on 25 - 27 Oct 2022, 24 - 26 May 2022, 4 - 6 Apr 2022, 22 – 24 Nov 2021 and 22 - 24 Mar 2021.

Learning outcomes

Participants will understand the new constructs and extensions in SystemVerilog which help to capture designer intent. You will learn to apply these to improve your existing RTL Design process.

Who is the course for?

Digital IC Design engineers. A knowledge of the Verilog language is a prerequisite.


Day 1
• Data types
• Modules
• Hierarchy
• Procedural blocks
• Assignments
• Tasks & Functions
• Finite State Machines
Day 2
• SV Data types, Arrays, Structures
• SV Procedural Blocks
• SV RTL Programming
• SV Hierarchy
• SV Tasks & Functions
• Miscellaneous Enhancements
• Interfaces
Day 3
• SV Assertions:
• Immediate & Concurrent
• Sequences & Properties:
• Blocks, Operators
• Methods & Arguments
• Local variables
• Using Assertions:
• Directives (assert & cover)
• Bind
• Multi-clock Assertions

Trainer Profile

Nigel Woolaway is President and co-founder of Leading Edge based in Milan. Nigel initially worked as a designer on military and commercial communication systems and started developing verification methodologies for digital ASIC and full custom designs in 1983. He has since held various engineering and management roles in the field of design and verification at OEMs and EDA providers. Nigel has trained hundreds of engineers on three continents in the usage of VHDL, Verilog, SystemVerilog and UVM. In addition to training Nigel provides consulting services on UVM testbench development to companies in Europe and the Middle East.

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